(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is provided with a data bus with an I/O terminals having a plurality of I/O pins for input and output purposes.
(2) Description of the Related Art
A semiconductor memory device of the kind to which the present invention relates comprises, as shown in FIG. 1, an I/O terminal 501 for input and output uses, a DATA-IN buffer 502, a DATA-OUT buffer 503, a distributing circuit 504, a coincidence circuit 505, data buses 506.sub.1, 506.sub.2, a decoder circuit 507, a sense amplifier circuit 508, and a memory cell array 509. The data bus 506.sub.1 is provided between the I/O terminal 501 and the distributing circuit 504, and the data bus 506.sub.2 is provided between the distributing circuit 504 and the decoder circuit 507.
When the data is written in the memory IC, the electric data signal of either "High" or "Low" is inputted to the I/O terminal 501 externally of the memory IC and, at the same time, an IN signal to the DATA-IN buffer 502 is made "Low". In this way, the DATA-IN buffer 502 is activated and the electric data signal is transferred to the data bus 506.sub.1. Also, by a select signal CA, the decoder circuit 507 is selected and the data is kept in the memory cell array 509 through the sense amplifier 508 of each memory. For outputting the data written in, the memory cell data is amplified by the sense amplifier 508, and the data signal line within the data bus 506.sub.2 and the memory cell within the memory cell array are selected by the decoder circuit 507.
For outputting the data, an OUT signal to the DATA-OUT buffer 503 is made "Low". Then, the DATA-OUT buffer 503 becomes activated, and the signal of the data bus 506.sub.1 is amplified and is outputted from the I/O terminal 501 to outside the memory IC.
For conducting the electrical testing of the memory IC, it is necessary to arrange that the I/O pins of the memory IC correspond to the driver/comparator pins of a testing means on a pin-to-pin basis, and a number of I/O pins of the memory IC are respectively connected to the driver/comparator pins of the same number in the testing means. Therefore, depending on the number of driver/comparator pins of the testing means, there will be a limit in the number of I/O pins, among a number of I/O pins in the memory IC, with which the measurement can be carried out simultaneously.
In the prior art memory device shown in FIG. 1, in order to increase the number of I/O pins with which the measurement can be made simultaneously, there are provided the distributing circuit 504 and the coincidence circuit 505.
The distributing circuit 504 shown in FIG. 2 is constituted by NMOS gates 601, 603 and 605 to which a TE signal to indicate a test mode of a gate is commonly applied, and NMOS gates 602, 604 and 606 to the gates of which an NO signal to indicate a normal state is commonly applied. The distributing circuit 504 controls a state of connections between data bus signal lines DB1-DB4 constituting a data bus 506.sub.1 and data bus signal lines DBA1-DBA4 constituting a data bus 506.sub.2.
The data bus signal line DB1 is connected to each of sources of the NMOS gates 601, 603 and 605, and is connected to the data bus signal line DBA1. The data bus signal lines DB2-DB4 are respectively connected to the sources of the NMOS gates 602, 604 and 606. The drains of the NMOS gates 601 and 602, gates 603 and 604, gates 605 and 606 are respectively connected with each other, thereby being connected to the data bus signal lines DBA2-DBA4.
In the distributing circuit 504 structured as above, when the TE signal which indicates a test mode status is made "Low" and the NO signal which indicates a normal state is made "High", the NMOS gates 602, 604 and 606 to which the NO signal is applied turn to a conductive state, and the NMOS gates 601, 603 and 605 to which the TE signal is applied turn to a non-conductive state. Consequently, the data bus signal lines DB1-DB4 are respectively connected to the data bus signal lines DBA1-DBA4 whereby the content of the data bus 5061 and that of the data bus 506.sub.2 will become the same.
When the NO signal is made "Low" and the TE signal is made "High", the NMOS gates 602, 604 and 606 to which the NO signal is applied turn to a non-conductive state, and the NMOS gates 601, 603 and 605 to which the TE signal is applied turn to a conductive state, whereby one data bus signal line DB1 is connected to a plurality of data bus signal lines DBA1-DBA4 and the data of four memory cells are stored simultaneously.
In the above prior art example, in the state in which one data bus signal line DB1 is connected to a plurality of data bus signal lines DBA1-DBA4, the electrical testing is carried out as to whether the memory operation is normal or not.
The electrical testing is carried out under the state in which the stored contents in each of the memory cells within the memory cell array 509 are made all either "High" or "Low". When the stored contents in each memory cell are outputted to the outside of the memory IC, the data stored in each memory cell are outputted to the data bus signal lines DBA1-DBA4 and inputted into the coincidence circuit 505. When the TE signal is "High", the coincidence circuit 505 operates, and determines whether all the stored contents in the memory cells are in coincidence with the levels preset. When in coincidence, "High" is outputted, and when not in coincidence, "Low" is outputted to the DATA-OUT buffer 503. At the DATA-OUT buffer 503, when the output of the coincidence circuit 505 is "High", the DBA1 data is amplified, and the amplified data is outputted to the outside of the memory IC from the I/O terminal 501. When such output is "Low", "High-z" (intermediate potential) is outputted from the I/O terminal 501. The operator of the device tests the output of the I/O terminal 501 thereby confirming any abnormality in the memory operation.
In the conventional memory IC explained above, it is so arranged that one data bus connected to the I/O terminal is connected to a plurality of data buses and that, in the case of the non-coincidence, the outputs of the plurality of data buses are outputted through one data bus. Thus, in the case where an output of a particular data bus is defective, it is not possible to confirm the reading and writing operation in the particular memory cells associated to the data bus, so that the entire data bus is judged defective.